The present disclosure relates generally to design, layout, testing, and fabrication of an integrated circuit and, more particularly, to determining parasitic resistance and capacitance of a layout of an integrated circuit (IC).
In designing an integrated circuit, after logic design is completed (e.g., register-transfer level (RTL) design), physical layout design is performed by placing and routing an integrated circuit provided by the logic design. Based upon the physical layout of an integrated circuit device (e.g., chip), various procedures are performed to ensure that the device will function appropriately and/or to better understand the performance of the device, including, for example, the delay time. These procedures typically include a layout parameter extraction (LPE) process performed for the layout design of the IC.
In an LPE process, extraction (e.g., calculation) of parasitic parameters such as, parasitic resistance and/or parasitic capacitance (hereinafter described as RC parameters), is performed. The parasitic resistance and/or capacitance are associated with interconnect patterns (e.g., conductive paths of an integrated circuit). Typically, the LPE process is accomplished by an LPE tool which is provided with a library for a given technology; the library includes interconnect patterns typically used in designing an IC and associated RC parameters. The library is used by the LPE tool to extract the RC parameters of a layout of an IC and thus, to predict the RC parameters of a fabricated IC. However, conventional methods for prediction of RC parameters are typically inaccurate. By way of example, the actual features (e.g., interconnect patterns) printed on a substrate often vary from the features as they are drawn in a layout design. This difference may result in inaccuracies of the RC parameters predicted by extraction of the RC parameters from a layout design of an IC, as compared to the RC parameters associated with the fabricated IC chip. Any inaccuracies in the predicted RC parameters can lead to inaccuracies in other IC parameter such as delay time.
As such an improved extraction of electric parameters of an interconnect pattern is desired.